(1) Field of the Invention
The present invention relates to a semiconductor integrated circuit able to switch the operational mode of an internal circuit. More particularly, it relates to a semiconductor integrated circuit comprising a memory cell array which can be switched from a usual (or normal operational) mode to a test mode, or vice versa.
(2) Description of the Related Art
Recently, the capacity of a memory cell array has been increased when a memory cell array having a large capacity (e.g., 1 (mega words).times.1 (bit)) is tested, the time needed for successively writing test data to each of the memory cells, and for successively reading test data from each of the memory cells, is increased. For example, if a test of a dynamic RAM having the above capacity and a cycle time of about 260 nano seconds is carried out using a March pattern (a well known test pattern), a test time of about 3.2 seconds is needed for carrying out the above test, and thus, the test time is increased according to the increase of the kinds of tests needed, and further, the cost of carrying out these tests is increased.
Thus, in order to test a memory cell array having a large capacity within a comparatively short time, the memory cell array is divided into several memory blocks, and each memory block is connected to a data input terminal and a data output terminal through a functional block for usual operation, which functions when the memory cell array operates in a usual mode, and a functional block for testing which functions when the memory cell array operates in a test mode. The functional block for a usual operation usually comprises a decoder for selecting one of the memory blocks.
Thus, in a write mode, predetermined write data is written to a predetermined memory cell arranged in the memory block selected by the decoder provided in the functional block for a usual operation. On the other hand, in a read mode, data written in a predetermined memory cell arranged in the memory block selected by the above decoder is output as read data.
Further, when a test for the memory cell array is carried out, the above circuits formed through the functional block for a usual operation are switched to the circuits formed through the functional block for testing, and the test data is simultaneously written to each of the corresponding memory cells arranged in each of the memory blocks, through the functional block for testing. Thus, in a test mode, it is possible to simultaneously carry out a test for all memory blocks within a relatively short time.
In the semiconductor integrated circuit having a construction such as above, it is necessary to provide a terminal for supplying a signal for switching the operational mode of the memory cell array from the outside, e.g., for switching the memory cell array from a usual mode to a test mode, or vice versa.
However, the number of terminals which can be provided in the package receiving the chip of the semiconductor integrated circuit is limited, and therefore, it is difficult to provide an exclusive terminal in the package for receiving the signal for switching the operational mode of the memory cell array from the outside and thus carry out the test for the memory cell array after the chip has been received in the package, especially when the capacity of the memory cell array has been increased.
Accordingly, it has been proposed to supply an input signal from the outside, this input signal having a potential set to a different value in the test mode from that of the input signal supplied in a usual mode, by using an existing terminal provided in the package (e.g., an address terminal connected to the above decoder for selecting one of the memory blocks), and to switch the operational mode of the memory cell array from a usual mode to a test mode, or vice versa, in accordance with an signal output by a voltage detecting circuit which detects the potential of the input signal.
However, in the conventional voltage detecting circuit, as the potential of the input signal is detected by the circuit in which a predetermined number of transistors is connected in series, the shift value due to the variation of the characteristics of each of the series connected transistors may be serially superimposed, and as a result, the correct value of the potential of the input signal cannot be detected. Accordingly, the signal for switching the operational mode of the memory cell array will be incorrectly output, even when each of the above shift values is small.
Therefore, according to the above voltage detecting circuit, a problem arises in that it is necessary to supply the input signal having a comparatively high value potential (e.g., 8 or 9 volts) as the input signal supplied in a test mode, to prevent the above incorrect operation, even when the potential of the input signal is lower than V.sub.CC (5 volts), for example, in the usual mode.
Further, in the above conventional circuit, as the input signal is continuously supplied from the outside, the potential of the input signal may often change, due to variations of the power supply potential and noise superimposed on the input signal.
Therefore, another problem arises in that the operational mode switched by the output signal of the voltage detecting circuit becomes unsteady due to the above change of the potential of the input signal. Also, in the above conventional circuit, a predetermined current continuously flows through the circuit during the test mode, for example, and therefore the power consumption tends to increase.